Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device and a method for forming the same.
With the increasing degree of integration of semiconductor devices, the design rule is being gradually reduced. As the design rule is reduced, the development of highly-integrated semiconductor memory devices (for example, a Dynamic Random Access Memory (DRAM)) is reaching its physical limits. Therefore, research for reducing a unit area of a cell storing one bit (1 bit) of data is being conducted. Recently, the unit cell design implementation has transitioned from a 8F2-sized unit cell for storing one bit to a 6F2-sized or 4F2-sized unit cell, so that a high-density cell structure can be configured.
In order to construct a transistor having the 4F2-sized unit cell, it is necessary for a junction part corresponding to the source and drain part to be in the 1F2-sized format. To accomplish this, many developers and companies are conducting intensive research into a cell transistor including a vertical channel in which the source and the drain can be formed within the 1F2-sized format. For a cell transistor including a vertical channel, the source region and the drain region of the transistor capable of operating the cell are formed at lower and upper parts, respectively, and the transistor is operated through a vertical-shaped channel. In a device with these features, the source and drain regions that run horizontally within the 8F2-sized unit cell are located at upper and lower parts in such a manner that the source and drain regions are configured in the form of a vertical structure, so that the cell transistor can be operated within the 4F2-sized unit cell. However, a cell transistor structure having such a vertical channel is difficult to fabricate, and it is very difficult to form the cell transistor structure due to structural complexity.